例句與造句

1. Based on the addition algorithm , the design was optimized by the method of scan chain control and iterative invoke and realized 14 kinds of large - number operations such as addition , subtraction , multiplication , division , module addition , module multiplication , module exponential , etc
   基于簡單的加法操作，采用掃描鏈控制、迭代調(diào)用等方法對設(shè)計進行優(yōu)化，實現(xiàn)了14種基本的大數(shù)運算功能。
2. First , the low testing power dft solution - - scan array architecture are presented . in the scan array , the inserted wrapper and paralleled leaf scan chain reduce the testing power as low as the power dissipation in the normal working mode
   首先，從優(yōu)化測試功耗的角度出發(fā)提出了掃描陣列結(jié)構(gòu)，通過加入wrapper測試控制結(jié)構(gòu)以及構(gòu)建并行化的分支掃描鏈，有效地將測試功耗降低到與正常工作功耗相當(dāng)?shù)牧考墶?
3. Chapter two detailedly presents the design of the boundary scan testing system which is in accordance with ieee . 1149 . correspondingly two special - used data registers are added , one of which is the scanning chain register and the other is the child scanning chain control - register
   文中第二章按照ieee . 1149標(biāo)準(zhǔn)詳細(xì)設(shè)計了邊緣掃描測試系統(tǒng)，相應(yīng)增加了兩個專用數(shù)據(jù)寄存器，其中一個為掃描鏈寄存器，一個為掃描子鏈控制寄存器。
4. During test , some registers in the processor are converted into scan chains to improve controllability of the circuit , the adders in the processor are used as test generators , and the produced test patterns can detect any combinational faults within every basic building cell of fft processor
   測試時，該方案將處理器中的寄存器作為掃描鏈提高了其可控性，利用其中的加法器作為測試生成，生成的測試矢量能偵測處理器每個基本組成單元內(nèi)部的任意組合失效。
5. It's difficult to find scan chain in a sentence. 用scan chain造句挺難的